Generally, memory refers to the physical devices used to store data or programs (sequences of instructions) on a temporary or permanent basis for use in an electronic digital computing device. Computing devices represent information in binary code, written as sequences of 0s and 1s. Each binary digit (or “bit”) may be stored by any physical system that can be in either of two stable states, to represent 0 and 1. This could be an on-off switch, an electrical capacitor that can store or lose a charge, a magnet with its polarity up or down, or a surface that can have a pit or not. Today, capacitors and transistors, functioning as tiny electrical switches, are used for temporary storage, and either disks or tape with a magnetic coating, or plastic discs with patterns of pits are used for long-term storage. Primary computing memory makes use of integrated circuits consisting of silicon-based transistors. There are two main types of memory: volatile and non-volatile.
Volatile memory is a kind of computing memory that requires power to maintain the stored information. Most modern semiconductor volatile memory is either Static Random Access Memory (SRAM) or dynamic Random Access Memory (DRAM). SRAM retains its contents as long as the power is connected. SRAM is commonplace in small embedded systems, and it is used in many other systems too. A typical SRAM uses six transistors (6T) to store each memory bit. In addition to such 6T SRAM, other kinds of SRAM chips use 4 transistors (4T), 8 transistors (8T), or more transistors per bit.
As shown in FIG. 1, each bit in an SRAM is stored on a storage cell comprising four transistors P1 and N1, P2 and N2 that form two cross-coupled inverters, where both P-transistors P1 and P2 are connected to a power supply 103Vdd and both N-transistors N1 and N2 are connected to the ground signal 191. This storage cell has two stable states which are used to denote 0 and 1, which is the value at the point 1011 Q and 1012 QB respectively. Two additional transistors N3 and N4 serve to control the access to the signals 1011 Q and 1012 QB, which are controlled by a Word Line (104 WL). The controls for N3 and N4 determine whether the signals 1011 Q and 1012 QB should be connected to the bit lines: BL (1051 BL) and BLB (1052 BLB), which are used to transfer data in and out of the SRAM cell. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins.
An SRAM cell has three different states it can be in: sleep where the circuit is idle, reading when the data has been requested and writing when updating the contents. An SRAM performs the three different states (standby, read, write) as follows:
Sleep—If the word line 104 WL is not asserted, the transistors N3 and N4 disconnect the cell from the bit lines 1051 and 1052. The two cross coupled inverters formed by P1 and N1, P2 and N2 will continue to reinforce each other as long as they are connected to the power supply 103Vdd.Reading—Assume that the content of the memory is a 1, stored at 1011 Q. The read cycle is started by pre-charging both the bit lines 1051 BL and 1052 BLB to a logical 1, then asserting the word line 104 WL, enabling both the access transistors N3 and N4. The second step occurs when the values stored in 1011 Q and 1012 QB are transferred to the bit lines by leaving 1051 BL at its pre-charged value and discharging 1052 BLB through N2 and N4 to a logical 0 (i.e., eventually discharging through the transistor N2 as it is turned on because the 1011 Q is logically set to 1). On the 1051 BL side, the transistors P1 and N3 pull the bit line 1051 BL toward VDD, a logical 1 (i.e., eventually being charged by the transistor P1 as it is turned on because 1012 QB is logically set to 0). If the content of the memory was a 0, the opposite would happen and 1051 BL would be pulled toward 0 and 1052 BLB toward 1. In either event, 1051 BL and 1052 BLB will have a voltage small difference of delta between them. A sense amplifier (not shown) will sense which line has higher voltage and thus will tell whether there was 1 stored or 0. The higher the sensitivity of sense amplifier, the faster the speed of the read operation is.Writing—The start of a write cycle begins by applying the value to be written to the bit lines 1051 BL and 1052 BLB. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting 1051 BL to 0 and 1052 BLB to 1. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines 1051 BL and 1052 BLB. The line 104 WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors P1, N1, P2, and N2 in the cell itself, so that they can easily override the previous state of the cross-coupled inverters.
Multiple SRAM cells can be arranged to form an SRAM array. As shown in FIG. 2, the size of an SRAM with m address lines and n data lines is 2m words, or 2m×n bits. FIG. 2 gives an overview of an SRAM memory design for a single data bit input/output. A single address of n+m bits is split into m row addresses 109 and n column address 110. The row address is first decoded by the 107 row decoder, so that one out of 2m word lines 104 WL in the memory array is being selected. Most RAMs are built so that all cells in the same row are activated. Consequentially, all 2n bit line pairs forming the columns leaving the memory array now contain data. The column decoder 108 selects one of these line pairs based on the column address 110, as shown in FIG. 2 as the 100 SRAM cell being selected. The selected cell 100 has a structure shown in FIG. 1. The power supply of the SRAM cell 100 is connected to the same word line 104, therefore the power supply of the SRAM cell operates at the same voltage as the word line WL 104. Typically, the signals from the selected 100 SRAM cell are output of the signals 1011 Q and 1012 QB, as demonstrated in FIG. 1. The output signals from 1011 Q and 1012 QB are passed to 1051 BL and 1052 BLB respectively and are sense-amplified, and then put into the data read buffer (not shown). In addition, the control signals Read (112R), Write (113W), and Sleep (114S) pass through a controller to decide which operations to perform based on the values of 112R, 113W, and 114S. Finally signal 115 is the data out read from the signal 1011 Q for a Read operation and signal 116 is the data in which is write to the signal 1011 Q for a Write operation.
The drawings, schematics, and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.